1. Field of the Invention
The present invention relates to a gate-drain overlapped device (hereinafter referred to as "GOLD") and a method for fabricating the same. More particularly, the present invention relates to a GOLD comprising a silicide layer on the surface of a polysilicon gate conductive line, which results in a significant improvement in the resistance of a polysilicon gate conductive line and in uniform electrical properties, and to a method for fabricating the same.
2. Description of the Prior Art
In MOSFETs, the gate length has sharply been reduced with the progressive high integration of semiconductor devices. Reduction of the gate length into less than 0.5 .mu.m turned out to deleteriously affects the reliability and the breakdown voltage. Accordingly, a fundamental change in the structure of MOSFET as well as in operating voltage has been required for the high integration of semiconductor devices.
In response to the requirement, drain engineering methods such as double diffused drain (DDD) and lightly doped drain (LDD) were newly suggested, with the aim of improving the reliability of MOSFETs. However, the drain engineering methods are proven to be unable to bring about high reliability and good performance at an operating voltage of 5 V because there is a tradeoff between the transconductance and the breakdown voltage. This is attributed to the fact that the drain engineering methods intend to optimize only the length of n.sup.- diffusion region (In) and the density of n.sup.- diffusion region (Nd).
In the meanwhile, the overlapped length between the gate and the drain was recognized to be a very important factor in controlling the characteristics of device. Based on this recognition, GOLD was suggested as an optimized structure to satisfy high reliability, superior performance and high breakdown voltage, without accompaniment of the tradeoff.
While the LDD structure uses a weak gate-drain overlap effect, the GOLD structure takes advantage of a strong gate-drain overlap effect. An inverse T LDD (ITLDD) structure, a kind of GOLD, was suggested to solve the problem of hot carrier deterioration attributable to the weak gate-drain overlap effect.
Such GOLD can be improved in reliability through the reduction of the horizontal electromagnetic field and hot carrier injection by the vertical electromagnetic field which is generated by the overlapped gate having an optimized gate-drain overlapped length. Thus, GOLD is a structure that allows the gate-drain overlap length to be optimized.
In order to better understand the background of the invention, a description of a conventional fabrication method of ITLDD will be given in conjunction with FIGS. 1A to 1E.
As shown in FIG. 1A, a gate oxide film 2 is grown on a substrate 1, for example, a single crystal silicon substrate, by a thermal oxidation process, followed by the deposition of a relatively thick gate polysilicon layer 3, which will be used for a gate electrode later, on the gate oxide film 2 and then, by the formation of an oxide film 4 on the gate polysilicon layer 3.
With reference to FIG. 1B, the oxide film 4 is selectively etched using a photosensitive film pattern (not shown) formed over the oxide film 4 as a mask, and the exposed area of the polysilicon layer 3 is dry etched to a thickness of about 100 to 500 Angstrom. After removing the photosensitive film pattern, an n type impurity, for example, phosphorus is implanted, as indicated by arrows, at a low dose and a high implantation energy into the substrate 1 except for an area maintaining its original thickness.
With reference to FIG. 1C, a blanket oxide film is deposited over the resulting structure of FIG. 1B by a chemical deposition process and subjected to etch back, to form a spacer 5 at the side wall of the area of polysilicon layer maintaining its original thickness. As will be described, the spacer 5 will serve as a mask to offset the ion implantation for drain/source of n.sup.+, with the aim of optimizing the length of the n.sup.- diffusion region (Ln.sup.-) in which the drain/source is overlapped with a gate to be formed later.
With reference to FIG. 1D, a plasma etch process is undertaken to remove the unmasked area of the polysilicon layer 3, resulting in the formation of an inverse T polysilicon gate 7, followed by the ion implantation of an n type impurity, for example, arsenic, into the substrate 1 at a high dose and a low energy while the spacer 5 serving as a mask.
With reference to FIG. 1E, the already implanted ions are activated by a thermal treatment process, for example, rapid annealing process, to form the drain/source regions, each consisting of an n.sup.+ diffusion region 8 and an n.sup.- diffusion region 9 which surrounds the n.sup.+ diffusion region 8.
Therefore, the offset between the n.sup.+ source/drain region and the gate is removed because the n.sup.+ source/drain region is self-aligned with the inverse T gate 7 upon the ion implantation. In addition, the optimum length (Ln.sup.-) is readily determined by the width of the spacer 7.
A significant problem of the conventional fabrication method of ITLDD is that the transistor exhibits nonuniform electrical properties. When the polysilicon layer is etched to a thin thickness, the resulting polysilicon layer is not uniform in thickness because etch processes are not precise, in general. Thus, the LDD of n.sup.- ions which is formed by implanting n.sup.- ions through the nonuniformly thinned polysilicon layer into the substrate and activating n.sup.- ions, is not uniform in density and junction depth because of the nonuniform thickness of the polysilicon layer etched.
Typically, a silicide is formed between a gate and a drain/source to solve the increase of gate resistance attributable to diminution of device. The conventional fabrication method of ITLDD, however, cannot utilize this silicide process, having a great difficulty in improving the performance of the ITLDD transistor.